
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b)


-- Executing script file `cc_synth.ys' --

1. Executing Liberty frontend.
Imported 9 cell types from liberty file.

2. Executing Verilog-2005 frontend: pebble_alu.v
Parsing Verilog input from `pebble_alu.v' to AST representation.
Generating RTLIL representation for module `\pebble_alu'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: pebble_core.v
Parsing Verilog input from `pebble_core.v' to AST representation.
Generating RTLIL representation for module `\pebble_core'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: pebble_dmem.v
Parsing Verilog input from `pebble_dmem.v' to AST representation.
Generating RTLIL representation for module `\pebble_dmem'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: pebble_regs.v
Parsing Verilog input from `pebble_regs.v' to AST representation.
Generating RTLIL representation for module `\pebble_regs'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: pebble_rom.v
Parsing Verilog input from `pebble_rom.v' to AST representation.
Generating RTLIL representation for module `\pebble_rom'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: pebble_soc.v
Parsing Verilog input from `pebble_soc.v' to AST representation.
Generating RTLIL representation for module `\pebble_soc'.
Successfully finished Verilog frontend.

8. Executing HIERARCHY pass (managing design hierarchy).

8.1. Analyzing design hierarchy..
Top module:  \pebble_soc
Used module:     \pebble_core
Used module:         \pebble_dmem
Used module:         \pebble_alu
Used module:         \pebble_regs
Used module:     \pebble_rom

8.2. Analyzing design hierarchy..
Top module:  \pebble_soc
Used module:     \pebble_core
Used module:         \pebble_dmem
Used module:         \pebble_alu
Used module:         \pebble_regs
Used module:     \pebble_rom
Removed 0 unused modules.

9. Executing SYNTH pass.

9.1. Executing HIERARCHY pass (managing design hierarchy).

9.1.1. Analyzing design hierarchy..
Top module:  \pebble_soc
Used module:     \pebble_core
Used module:         \pebble_dmem
Used module:         \pebble_alu
Used module:         \pebble_regs
Used module:     \pebble_rom

9.1.2. Analyzing design hierarchy..
Top module:  \pebble_soc
Used module:     \pebble_core
Used module:         \pebble_dmem
Used module:         \pebble_alu
Used module:         \pebble_regs
Used module:     \pebble_rom
Removed 0 unused modules.

9.2. Executing PROC pass (convert processes to netlists).

9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$pebble_rom.v:11$81 in module pebble_rom.
Marked 2 switch rules as full_case in process $proc$pebble_regs.v:16$68 in module pebble_regs.
Marked 1 switch rules as full_case in process $proc$pebble_dmem.v:12$53 in module pebble_dmem.
Marked 1 switch rules as full_case in process $proc$pebble_core.v:38$47 in module pebble_core.
Marked 1 switch rules as full_case in process $proc$pebble_alu.v:14$1 in module pebble_alu.
Removed a total of 0 dead cases.

9.2.3. Executing PROC_INIT pass (extract init attributes).

9.2.4. Executing PROC_ARST pass (detect async resets in processes).

9.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\pebble_rom.$proc$pebble_rom.v:11$81'.
     1/2: $1\data[15:0]
     2/2: $0\data[15:0]
Creating decoders for process `\pebble_regs.$proc$pebble_regs.v:16$68'.
     1/4: $0\r0[7:0]
     2/4: $0\r3[7:0]
     3/4: $0\r2[7:0]
     4/4: $0\r1[7:0]
Creating decoders for process `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
     1/8: $0\m0[7:0]
     2/8: $0\m7[7:0]
     3/8: $0\m6[7:0]
     4/8: $0\m5[7:0]
     5/8: $0\m4[7:0]
     6/8: $0\m3[7:0]
     7/8: $0\m1[7:0]
     8/8: $0\m2[7:0]
Creating decoders for process `\pebble_core.$proc$pebble_core.v:38$47'.
     1/6: $0\cflag[0:0]
     2/6: $0\out_data[7:0]
     3/6: $0\zflag[0:0]
     4/6: $0\pc[4:0]
     5/6: $0\halted[0:0]
     6/6: $0\out_valid[0:0]
Creating decoders for process `\pebble_alu.$proc$pebble_alu.v:14$1'.
     1/6: $1\carry[0:0]
     2/6: $1\y[7:0]
     3/6: $1\wide[8:0]
     4/6: $0\carry[0:0]
     5/6: $0\y[7:0]
     6/6: $0\wide[8:0]

9.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\pebble_rom.\data' from process `\pebble_rom.$proc$pebble_rom.v:11$81'.
No latch inferred for signal `\pebble_alu.\wide' from process `\pebble_alu.$proc$pebble_alu.v:14$1'.
No latch inferred for signal `\pebble_alu.\y' from process `\pebble_alu.$proc$pebble_alu.v:14$1'.
No latch inferred for signal `\pebble_alu.\carry' from process `\pebble_alu.$proc$pebble_alu.v:14$1'.

9.2.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\pebble_regs.\r1' using process `\pebble_regs.$proc$pebble_regs.v:16$68'.
  created $dff cell `$procdff$259' with positive edge clock.
Creating register for signal `\pebble_regs.\r2' using process `\pebble_regs.$proc$pebble_regs.v:16$68'.
  created $dff cell `$procdff$260' with positive edge clock.
Creating register for signal `\pebble_regs.\r3' using process `\pebble_regs.$proc$pebble_regs.v:16$68'.
  created $dff cell `$procdff$261' with positive edge clock.
Creating register for signal `\pebble_regs.\r0' using process `\pebble_regs.$proc$pebble_regs.v:16$68'.
  created $dff cell `$procdff$262' with positive edge clock.
Creating register for signal `\pebble_dmem.\m2' using process `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
  created $dff cell `$procdff$263' with positive edge clock.
Creating register for signal `\pebble_dmem.\m1' using process `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
  created $dff cell `$procdff$264' with positive edge clock.
Creating register for signal `\pebble_dmem.\m3' using process `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
  created $dff cell `$procdff$265' with positive edge clock.
Creating register for signal `\pebble_dmem.\m4' using process `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
  created $dff cell `$procdff$266' with positive edge clock.
Creating register for signal `\pebble_dmem.\m5' using process `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
  created $dff cell `$procdff$267' with positive edge clock.
Creating register for signal `\pebble_dmem.\m6' using process `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
  created $dff cell `$procdff$268' with positive edge clock.
Creating register for signal `\pebble_dmem.\m7' using process `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
  created $dff cell `$procdff$269' with positive edge clock.
Creating register for signal `\pebble_dmem.\m0' using process `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
  created $dff cell `$procdff$270' with positive edge clock.
Creating register for signal `\pebble_core.\out_valid' using process `\pebble_core.$proc$pebble_core.v:38$47'.
  created $dff cell `$procdff$271' with positive edge clock.
Creating register for signal `\pebble_core.\halted' using process `\pebble_core.$proc$pebble_core.v:38$47'.
  created $dff cell `$procdff$272' with positive edge clock.
Creating register for signal `\pebble_core.\pc' using process `\pebble_core.$proc$pebble_core.v:38$47'.
  created $dff cell `$procdff$273' with positive edge clock.
Creating register for signal `\pebble_core.\zflag' using process `\pebble_core.$proc$pebble_core.v:38$47'.
  created $dff cell `$procdff$274' with positive edge clock.
Creating register for signal `\pebble_core.\out_data' using process `\pebble_core.$proc$pebble_core.v:38$47'.
  created $dff cell `$procdff$275' with positive edge clock.
Creating register for signal `\pebble_core.\cflag' using process `\pebble_core.$proc$pebble_core.v:38$47'.
  created $dff cell `$procdff$276' with positive edge clock.

9.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\pebble_rom.$proc$pebble_rom.v:11$81'.
Removing empty process `pebble_rom.$proc$pebble_rom.v:11$81'.
Found and cleaned up 3 empty switches in `\pebble_regs.$proc$pebble_regs.v:16$68'.
Removing empty process `pebble_regs.$proc$pebble_regs.v:16$68'.
Found and cleaned up 2 empty switches in `\pebble_dmem.$proc$pebble_dmem.v:12$53'.
Removing empty process `pebble_dmem.$proc$pebble_dmem.v:12$53'.
Found and cleaned up 5 empty switches in `\pebble_core.$proc$pebble_core.v:38$47'.
Removing empty process `pebble_core.$proc$pebble_core.v:38$47'.
Found and cleaned up 1 empty switch in `\pebble_alu.$proc$pebble_alu.v:14$1'.
Removing empty process `pebble_alu.$proc$pebble_alu.v:14$1'.
Cleaned up 12 empty switches.

9.3. Executing FLATTEN pass (flatten design).
Using template pebble_rom for cells of type pebble_rom.
Using template pebble_core for cells of type pebble_core.
Using template pebble_alu for cells of type pebble_alu.
Using template pebble_regs for cells of type pebble_regs.
Using template pebble_dmem for cells of type pebble_dmem.
<suppressed ~5 debug messages>
No more expansions possible.
Deleting now unused module pebble_rom.
Deleting now unused module pebble_regs.
Deleting now unused module pebble_dmem.
Deleting now unused module pebble_core.
Deleting now unused module pebble_alu.

9.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.
<suppressed ~13 debug messages>

9.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..
Removed 16 unused cells and 89 unused wires.
<suppressed ~21 debug messages>

9.6. Executing CHECK pass (checking for obvious problems).
checking module pebble_soc..
found and reported 0 problems.

9.7. Executing OPT pass (performing simple optimizations).

9.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.

9.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
<suppressed ~60 debug messages>
Removed a total of 20 cells.

9.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \pebble_soc..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $techmap\core.$procmux$226: \core.halted -> 1'1
      Replacing known input bits on port A of cell $techmap\core.$procmux$224: \core.halted -> 1'0
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~21 debug messages>

9.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \pebble_soc.
    New input vector for $reduce_or cell $techmap\core.alu.$procmux$250_ANY: { $techmap\core.$eq$pebble_core.v:28$16_Y $techmap\core.$eq$pebble_core.v:25$9_Y }
    New ctrl vector for $pmux cell $techmap\rom.$procmux$83: { $techmap\rom.$procmux$102_CMP $techmap\rom.$procmux$101_CMP $techmap\rom.$procmux$100_CMP $techmap\rom.$procmux$99_CMP $techmap\rom.$procmux$98_CMP $techmap\rom.$procmux$96_CMP $auto$opt_reduce.cc:132:opt_mux$280 $techmap\rom.$procmux$94_CMP $techmap\rom.$procmux$93_CMP $techmap\rom.$procmux$92_CMP $techmap\rom.$procmux$91_CMP $techmap\rom.$procmux$90_CMP $techmap\rom.$procmux$89_CMP $techmap\rom.$procmux$88_CMP $techmap\rom.$procmux$87_CMP $techmap\rom.$procmux$86_CMP $auto$opt_reduce.cc:132:opt_mux$278 $techmap\rom.$procmux$84_CMP }
  Optimizing cells in module \pebble_soc.
Performed a total of 2 changes.

9.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.7.6. Executing OPT_RMDFF pass (remove dff with constant values).

9.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..
Removed 0 unused cells and 19 unused wires.
<suppressed ~1 debug messages>

9.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.

9.7.9. Rerunning OPT passes. (Maybe there is more to do..)

9.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \pebble_soc..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~21 debug messages>

9.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \pebble_soc.
Performed a total of 0 changes.

9.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.7.13. Executing OPT_RMDFF pass (remove dff with constant values).

9.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..

9.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.

9.7.16. Finished OPT passes. (There is nothing left to do.)

9.8. Executing WREDUCE pass (reducing word size of cells).
Removed top 2 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$97_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$102_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$101_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$100_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$99_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$98_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$96_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$95_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$94_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$93_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$92_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$91_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$90_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$89_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell pebble_soc.$techmap\rom.$procmux$88_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell pebble_soc.$techmap\core.$add$pebble_core.v:44$49 ($add).
Removed top 3 bits (of 4) from port B of cell pebble_soc.$techmap\core.$ne$pebble_core.v:30$34 ($ne).
Removed top 1 bits (of 4) from port B of cell pebble_soc.$techmap\core.$eq$pebble_core.v:29$24 ($eq).
Removed top 1 bits (of 4) from port B of cell pebble_soc.$techmap\core.$eq$pebble_core.v:28$22 ($eq).
Removed top 1 bits (of 4) from port B of cell pebble_soc.$techmap\core.$eq$pebble_core.v:28$20 ($eq).
Removed top 2 bits (of 4) from port B of cell pebble_soc.$techmap\core.$eq$pebble_core.v:28$18 ($eq).
Removed top 2 bits (of 4) from port B of cell pebble_soc.$techmap\core.$eq$pebble_core.v:28$16 ($eq).
Removed top 1 bits (of 4) from port B of cell pebble_soc.$techmap\core.$eq$pebble_core.v:25$9 ($eq).
Removed top 3 bits (of 4) from port B of cell pebble_soc.$techmap\core.$eq$pebble_core.v:25$8 ($eq).
Removed top 1 bits (of 9) from port A of cell pebble_soc.$techmap\core.alu.$sub$pebble_alu.v:20$3 ($sub).
Removed top 1 bits (of 9) from port B of cell pebble_soc.$techmap\core.alu.$sub$pebble_alu.v:20$3 ($sub).
Removed top 1 bits (of 9) from port Y of cell pebble_soc.$techmap\core.alu.$sub$pebble_alu.v:20$3 ($sub).
Removed top 1 bits (of 9) from port A of cell pebble_soc.$techmap\core.alu.$add$pebble_alu.v:19$2 ($add).
Removed top 1 bits (of 9) from port B of cell pebble_soc.$techmap\core.alu.$add$pebble_alu.v:19$2 ($add).
Removed top 1 bits (of 9) from port Y of cell pebble_soc.$techmap\core.alu.$add$pebble_alu.v:19$2 ($add).
Removed top 1 bits (of 2) from port B of cell pebble_soc.$techmap\core.regs.$eq$pebble_regs.v:29$76 ($eq).
Removed top 1 bits (of 2) from port B of cell pebble_soc.$techmap\core.regs.$eq$pebble_regs.v:28$70 ($eq).
Removed top 1 bits (of 3) from port B of cell pebble_soc.$techmap\core.dmem.$eq$pebble_dmem.v:26$57 ($eq).
Removed top 1 bits (of 3) from port B of cell pebble_soc.$techmap\core.dmem.$eq$pebble_dmem.v:26$56 ($eq).
Removed top 2 bits (of 3) from port B of cell pebble_soc.$techmap\core.dmem.$eq$pebble_dmem.v:26$55 ($eq).
Removed top 1 bits (of 9) from wire pebble_soc.$techmap\core.alu.$add$pebble_alu.v:19$2_Y.

9.9. Executing PEEPOPT pass (run peephole optimizers).

9.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

9.11. Executing TECHMAP pass (map to technology primitives).

9.11.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

9.11.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~724 debug messages>

9.12. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module pebble_soc:
  creating $macc model for $techmap\core.$add$pebble_core.v:44$49 ($add).
  creating $macc model for $techmap\core.alu.$add$pebble_alu.v:19$2 ($add).
  creating $macc model for $techmap\core.alu.$sub$pebble_alu.v:20$3 ($sub).
  creating $alu model for $macc $techmap\core.alu.$sub$pebble_alu.v:20$3.
  creating $alu model for $macc $techmap\core.alu.$add$pebble_alu.v:19$2.
  creating $alu model for $macc $techmap\core.$add$pebble_core.v:44$49.
  creating $alu cell for $techmap\core.$add$pebble_core.v:44$49: $auto$alumacc.cc:474:replace_alu$282
  creating $alu cell for $techmap\core.alu.$add$pebble_alu.v:19$2: $auto$alumacc.cc:474:replace_alu$285
  creating $alu cell for $techmap\core.alu.$sub$pebble_alu.v:20$3: $auto$alumacc.cc:474:replace_alu$288
  created 3 $alu and 0 $macc cells.

9.13. Executing SHARE pass (SAT-based resource sharing).

9.14. Executing OPT pass (performing simple optimizations).

9.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.

9.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \pebble_soc..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~21 debug messages>

9.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \pebble_soc.
Performed a total of 0 changes.

9.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.14.6. Executing OPT_RMDFF pass (remove dff with constant values).

9.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..

9.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.

9.14.9. Finished OPT passes. (There is nothing left to do.)

9.15. Executing FSM pass (extract and optimize FSM).

9.15.1. Executing FSM_DETECT pass (finding FSMs in design).

9.15.2. Executing FSM_EXTRACT pass (extracting FSM from design).

9.15.3. Executing FSM_OPT pass (simple optimizations of FSMs).

9.15.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..

9.15.5. Executing FSM_OPT pass (simple optimizations of FSMs).

9.15.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

9.15.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

9.15.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

9.16. Executing OPT pass (performing simple optimizations).

9.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.

9.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.16.3. Executing OPT_RMDFF pass (remove dff with constant values).

9.16.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..

9.16.5. Finished fast OPT passes.

9.17. Executing MEMORY pass.

9.17.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

9.17.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..

9.17.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

9.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..

9.17.5. Executing MEMORY_COLLECT pass (generating $mem cells).

9.18. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..

9.19. Executing OPT pass (performing simple optimizations).

9.19.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.
<suppressed ~3 debug messages>

9.19.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.19.3. Executing OPT_RMDFF pass (remove dff with constant values).

9.19.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

9.19.5. Finished fast OPT passes.

9.20. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

9.21. Executing OPT pass (performing simple optimizations).

9.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.

9.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \pebble_soc..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~21 debug messages>

9.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \pebble_soc.
    Consolidated identical input bits for $pmux cell $techmap\rom.$procmux$83:
      Old ports: A=16'0000000000000000, B=288'000101000000101000011000000000010010000100000000001101100000000011000000000000111001000000000000000100000000000000010100000000010001110000000111111001000000000010010100000000010010010000000000100000000000000100111110000000001100000000001011100000000000000011100000000000001111000000000000, Y=\core.instr
      New ports: A=12'000000000000, B=216'000101001010000110000001001000010000001101100000110000000011100100000000000100000000000101000001000111000111111001000000100101000001001001000000100000000001001111100000110000001011100000000000111000000000111100000000, Y={ \core.instr [15:8] \core.instr [3:0] }
      New connections: \core.instr [7:4] = 4'0000
  Optimizing cells in module \pebble_soc.
Performed a total of 1 changes.

9.21.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.21.6. Executing OPT_RMDFF pass (remove dff with constant values).

9.21.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..

9.21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.

9.21.9. Rerunning OPT passes. (Maybe there is more to do..)

9.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \pebble_soc..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~21 debug messages>

9.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \pebble_soc.
Performed a total of 0 changes.

9.21.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.21.13. Executing OPT_RMDFF pass (remove dff with constant values).

9.21.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..

9.21.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.

9.21.16. Finished OPT passes. (There is nothing left to do.)

9.22. Executing TECHMAP pass (map to technology primitives).

9.22.1. Executing Verilog-2005 frontend: <techmap.v>
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

9.22.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod\_90_pmux\WIDTH=12\S_WIDTH=18 for cells of type $pmux.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $logic_or.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $reduce_or.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=6 for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $and.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=8 for cells of type $lcu.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=5 for cells of type $lcu.
No more expansions possible.
<suppressed ~558 debug messages>

9.23. Executing OPT pass (performing simple optimizations).

9.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.
<suppressed ~737 debug messages>

9.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
<suppressed ~531 debug messages>
Removed a total of 177 cells.

9.23.3. Executing OPT_RMDFF pass (remove dff with constant values).

9.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..
Removed 38 unused cells and 348 unused wires.
<suppressed ~39 debug messages>

9.23.5. Finished fast OPT passes.

9.24. Executing ABC pass (technology mapping using ABC).

9.24.1. Extracting gate netlist of module `\pebble_soc' to `<abc-temp-dir>/input.blif'..
Extracted 827 gates and 941 wires to a netlist network with 112 inputs and 112 outputs.

9.24.1.1. Executing ABC.
Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 17 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + retime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

9.24.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:       12
ABC RESULTS:            ANDNOT cells:       94
ABC RESULTS:              AOI3 cells:       20
ABC RESULTS:              AOI4 cells:        1
ABC RESULTS:               MUX cells:      337
ABC RESULTS:              NAND cells:        9
ABC RESULTS:               NOR cells:       17
ABC RESULTS:               NOT cells:      110
ABC RESULTS:              OAI3 cells:       33
ABC RESULTS:              OAI4 cells:       17
ABC RESULTS:                OR cells:       82
ABC RESULTS:             ORNOT cells:       30
ABC RESULTS:              XNOR cells:       14
ABC RESULTS:               XOR cells:       13
ABC RESULTS:        internal signals:      717
ABC RESULTS:           input signals:      112
ABC RESULTS:          output signals:      112
Removing temp directory.

9.25. Executing OPT pass (performing simple optimizations).

9.25.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module pebble_soc.
<suppressed ~6 debug messages>

9.25.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\pebble_soc'.
Removed a total of 0 cells.

9.25.3. Executing OPT_RMDFF pass (remove dff with constant values).

9.25.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..
Removed 1 unused cells and 431 unused wires.
<suppressed ~27 debug messages>

9.25.5. Finished fast OPT passes.

9.26. Executing HIERARCHY pass (managing design hierarchy).

9.26.1. Analyzing design hierarchy..
Top module:  \pebble_soc

9.26.2. Analyzing design hierarchy..
Top module:  \pebble_soc
Removed 0 unused modules.

9.27. Printing statistics.

=== pebble_soc ===

   Number of wires:                827
   Number of wire bits:            998
   Number of public wires:          39
   Number of public wire bits:     210
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                900
     $_ANDNOT_                      94
     $_AND_                         12
     $_AOI3_                        20
     $_AOI4_                         1
     $_DFF_P_                      112
     $_MUX_                        337
     $_NAND_                         9
     $_NOR_                         17
     $_NOT_                        109
     $_OAI3_                        33
     $_OAI4_                        17
     $_ORNOT_                       30
     $_OR_                          82
     $_XNOR_                        14
     $_XOR_                         13

9.28. Executing CHECK pass (checking for obvious problems).
checking module pebble_soc..
found and reported 0 problems.

10. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell DFF (noninv, pins=3, area=6.00) is a direct match for cell type $_DFF_P_.
  create mapping for $_DFF_N_ from mapping for $_DFF_P_.
  final dff cell mappings:
    DFF _DFF_N_ (.C(~C), .D( D), .Q( Q));
    DFF _DFF_P_ (.C( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    unmapped dff cell: $_DFF_PN0_
    unmapped dff cell: $_DFF_PN1_
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    unmapped dff cell: $_DFFSR_NNN_
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_
Mapping DFF cells in module `\pebble_soc':
  mapped 112 $_DFF_P_ cells to \DFF cells.

11. Executing ABC pass (technology mapping using ABC).

11.1. Extracting gate netlist of module `\pebble_soc' to `<abc-temp-dir>/input.blif'..
Extracted 788 gates and 900 wires to a netlist network with 112 inputs and 112 outputs.

11.1.1. Executing ABC.
Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w /tmp/cc-chip-test-ETadfO/cc_cells.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Warning: Templates are not defined.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF".
ABC: Library "cc_cells" from "/tmp/cc-chip-test-ETadfO/cc_cells.lib" has 8 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec
ABC: Memory =    0.02 MB. Time =     0.00 sec
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + retime -D 20000 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf -D 20000 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 

11.1.2. Re-integrating ABC results.
ABC RESULTS:              AND2 cells:      172
ABC RESULTS:               BUF cells:       48
ABC RESULTS:               INV cells:       22
ABC RESULTS:             NAND2 cells:      284
ABC RESULTS:              NOR2 cells:       98
ABC RESULTS:               OR2 cells:       93
ABC RESULTS:             XNOR2 cells:       11
ABC RESULTS:              XOR2 cells:        9
ABC RESULTS:        internal signals:      676
ABC RESULTS:           input signals:      112
ABC RESULTS:          output signals:      112
Removing temp directory.

12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \pebble_soc..
Removed 48 unused cells and 927 unused wires.
<suppressed ~52 debug messages>

13. Executing CHECK pass (checking for obvious problems).
checking module pebble_soc..
found and reported 0 problems.
15. Executing Verilog backend.
Dumping module `\pebble_soc'.

16. Executing JSON backend.

End of script. Logfile hash: a671237955
CPU: user 0.64s system 0.04s, MEM: 22.06 MB total, 16.53 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 19% 18x opt_clean (0 sec), 13% 15x opt_expr (0 sec), ...
